Msr; Figure 10-37. Machine State Register (Msr) - IBM PPC440X5 CPU Core User Manual

MSR

Machine State Register
PPC440x5 CPU Core User's Manual
MSR
Supervisor R/W
See Machine State Register (MSR) on page 165.
0

Figure 10-37. Machine State Register (MSR)

0:12 Reserved
Wait State Enable
0 The processor is not in the wait state.
13 WE
1 The processor is in the wait state.
Critical Interrupt Enable
0 Critical Input and Watchdog Timer interrupts are
disabled.
14 CE
1 Critical Input and Watchdog Timer interrupts are
enabled.
15 Reserved
External Interrupt Enable
0 External Input, Decrementer, and Fixed Interval
Timer interrupts are disabled.
16 EE
1 External Input, Decrementer, and Fixed Interval
Timer interrupts are enabled.
Problem State
0 Supervisor state (privileged instructions can be
executed)
17 PR
1 Problem state (privileged instructions can not be
executed)
Floating Point Available
0 The processor cannot execute floating-point
18 FP instructions
1 The processor can execute floating-point
instructions
Machine Check Enable
0 Machine Check interrupts are disabled
19 ME
1 Machine Check interrupts are enabled.
Floating-point exception mode 0
0 If MSR[FE1] = 0, ignore exceptions mode; if
MSR[FE1] = 1, imprecise nonrecoverable mode
20 FE0
1 If MSR[FE1] = 0, imprecise recoverable mode; if
MSR[FE1] = 1, precise mode
Debug Wait Enable
0 Disable debug wait mode.
21 DWE
1 Enable debug wait mode.
Debug interrupt Enable
0 Debug interrupts are disabled.
22 DE
1 Debug interrupts are enabled.
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EE
FP
WE
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CE ME
PR
DE IS
FE0
DWE FE1
If MSR[WE] = 1, the processor remains in the wait
state until an interrupt is taken, a reset occurs, or
an external debug tool clears WE.
Preliminary
31
DS
regsumm440core.fm.
September 12, 2002