Dcbi - IBM PPC440X5 CPU Core User Manual

Preliminary

dcbi

Data Cache Block Invalidate
dcbi RA, RB
31
0 6
EA (RA|0) + (RB)
DCBI(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is in the data cache, the data block is marked invalid, regardless of whether or not
the memory page referenced by the EA is marked as cacheable. If modified data existed in the data block
prior to the operation of this instruction, that data is lost.
If the data block at the EA is not in the data cache, no operation is performed.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
Execution of this instruction is privileged.
Exceptions
This instruction is considered a "store" with respect to Data Storage exceptions. See Data Storage Interrupt
on page 181 for more information.
This instruction is considered a "store" with respect to data address compare (DAC) Debug exceptions. See
Debug Interrupt on page 195 for more information.
instrset.fm.
September 12, 2002
RA RB
11 16
Data Cache Block Invalidate
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dcbi
31