Tlb Management Instructions - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
The instruction shadow TLB (ITLB) contains four entries, while the data shadow TLB (DTLB) contains eight.
There is no latency associated with accessing the shadow TLB arrays, and instruction execution continues in
a pipelined fashion as long as the requested address is found in the shadow TLB. If the requested address is
not found in the shadow TLB, the instruction fetch or data storage access is automatically stalled while the
address is looked up in the UTLB. If the address is found in the UTLB, the penalty associated with the miss in
the shadow array is three cycles. If the address is also a miss in the UTLB, then an Instruction or Data TLB
Miss exception is reported.
The replacement of entries in the shadow TLB's is managed by hardware, in a round-robin fashion. Upon a
shadow TLB miss which leads to a UTLB hit, the hardware will automatically cast-out the oldest entry in the
shadow TLB and replace it with the new translation.
The hardware will also automatically invalidate all of the entries in both of the shadow TLB's upon any context
synchronization (see Context Synchronization on page 82). Context synchronizing operations include the
following:
• Any interrupt (including Machine Check)
• Execution of isync
• Execution of rfi, rfci, or rfmci
• Execution of sc
Note that there are other "context changing" operations which do not cause automatic context synchroniza-
tion in the hardware. For example, execution of a tlbwe instruction changes the UTLB contents but does not
cause a context synchronization and thus does not invalidate or otherwise update the shadow TLB entries. In
order for changes to the entries in the UTLB (or to other address-related resources such as the PID) to be
reflected in the shadow TLB's, software must ensure that a context synchronizing operation occurs prior to
any attempt to use any address associated with the updated UTLB entries (either the old or new contents of
those entries). By invalidating the shadow TLB arrays, a context synchronizing operation forces the hardware
to refresh the shadow TLB entries with the updated information in the UTLB as each memory page is
accessed.
Note: Of the items in the preceding list of shadow TLB invalidating operations, the Machine Check interrupt
is not architecturally required to be context synchronizing, and thus is not guaranteed to cause invalidation of
any shadow TLB arrays on implementations other than the PPC440x5. Consequently, software which is
intended to be portable to other implementations should not depend on this behavior, and should insert the
appropriate architecturally-defined context synchronizing operation as necessary for desired operation.

5.9 TLB Management Instructions

The processor does not imply any format for the page tables or the page table entries. Software has signifi-
cant flexibility in organizing the size, location, and format of the page table, and in implementing a custom
TLB entry replacement strategy. For example, software can "lock" TLB entries that correspond to frequently
used storage, so that those entries are never cast out of the TLB, and TLB Miss exceptions to those pages
never occur.
In order to enable software to manage the TLB, a set of TLB management instructions is implemented within
the PPC440x5 core. These instructions are described briefly in the sections which follow, and in detail in
Chapter 9, "Instruction Set." In addition, the interrupt mechanism provides resources to assist with software
handling of TLB-related exceptions. One such resource is Save/Restore Register 0 (SRR0), which provides
the exception-causing address for Instruction TLB Error and Instruction Storage interrupts. Another resource
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September 12, 2002