Interrupt Definitions - IBM PPC440X5 CPU Core User Manual

Preliminary
Instruction Cache Parity Error
0 Exception not caused by I-cache parity error
5 ICP
1 Exception caused by I-cache parity error
Data Cache Search Parity Error
0 Exception not caused by DCU Search parity error
6 DCSP
1 Exception caused by DCU Search parity error
Data Cache Flush Parity Error
0 Exception not caused by DCU Flush parity error
7 DCFP
1 Exception caused by DCU Flush parity error
Imprecise Machine Check Exception
0 No imprecise machine check exception occurred.
8 IMPE
1 Imprecise machine check exception occurred.
9:31 Reserved
6.5 Interrupt Definitions
Table 6-2 provides a summary of each interrupt type, in the order corresponding to their associated IVOR
register. The table also summarizes the various exception types that may cause that interrupt type; the clas-
sification of the interrupt; which ESR bit(s) can be set, if any; and which mask bit(s) can mask the interrupt
type, if any.
Detailed descrptions of each of the interrupt types follow the table..
Table 6-2. Interrupt and Exception Types
IVOR Interrupt Type
IVOR0 Critical Input
IVOR1 Machine Check
IVOR2 Data Storage
IVOR3 Instruction Storage
IVOR4 External Input
IVOR5 Alignment
intrupts.fm.
September 12, 2002
Exception Type
Critical Input
Instruction Machine Check
Data Machine Check
TLB Machine Check
Read Access Control
Write Access Control
Cache Locking
Byte Ordering
Execute Access Control
Byte Ordering
External Input
Alignment
Set if and only If the DCU parity error was dis-
covered during a DCU Search operation.
See Data Cache Parity Operations on
page 129.
Set if and only If the DCU parity error was dis-
covered during a DCU Flush operation.
See Data Cache Parity Operations on
page 129.
Set if a machine check exception occurs that
sets MCSR[MCS] (or would if it were not
already set) and MSR[ME] = 0.
ESR
(See Note 4)
x x
[MCI]
x [FP,AP]
x ST,[FP,AP]
x {DLK ,DLK
0
x BO,[ST],[FP,AP]
x
x BO
x
x [ST],[FP,AP]
User's Manual
PPC440x5 CPU Core
CE 1
ME 2
ME 2
ME 2
}
1
5
6
EE 1
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