Data Tlb Error Interrupt - IBM PPC440X5 CPU Core User Manual

Preliminary
Critical Save/Restore Register 0 (CSRR0)
Set to the effective address of the next instruction to be executed.
Critical Save/Restore Register 1 (CSRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
ME Unchanged.
All other MSR bits set to 0.
Programming Note: Software is responsible for clearing the Watchdog Timer exception

6.5.14 Data TLB Error Interrupt

A Data TLB Error interrupt may occur when no higher priority exception exists and a Data TLB Miss exception
is presented to the interrupt mechanism. A Data TLB Miss exception occurs when a load, store, icbi, icbt,
dcbst, dcbf, dcbz, dcbi, dcbt, or dcbtst instruction attempts to access a virtual address for which a valid
TLB entry does not exist. See Chapter 5, "Memory Management" for more information on the TLB.
Programming Note: The instruction cache management instructions icbi and icbt are
If a stwcx. instruction causes a Data TLB Miss exception, and the processor does not have the reservation
from a lwarx instruction, then a Data TLB Error interrupt still occurs.
If a Data TLB Miss exception occurs on any of the following instructions, then the instruction is treated
as a no-op, and a Data TLB Error interrupt does not occur.
lswx or stswx with a length of zero (although the target register of lswx will be undefined)
•
• icbt
• dcbt
• dcbtst
For all other instructions, if a Data TLB Miss exception occurs, then execution of the instruction causing the
exception is suppressed, a Data TLB Error interrupt is generated, the interrupt processing registers are
updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at
address IVPR[IVP] || IVOR13[IVO] || 0b0000.
intrupts.fm.
September 12, 2002
status by writing to TSR[WIS], prior to reenabling MSR[CE], in order to
avoid another, redundant Watchdog Timer interrupt.
treated as "loads" from the addressed byte with respect to address
translation and protection, and therefore use MSR[DS] rather than
MSR[IS] as part of the calculated virtual address when searching the
TLB to determine translation for their target storage address.
Instruction TLB Miss exceptions are associated with the fetching of
instructions not with the execution of instructions. Data TLB Miss
exceptions are associated with the execution of instruction cache
management instructions, as well as with the execution of load, store,
and data cache management instructions.
User's Manual
PPC440x5 CPU Core
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