Stswx - IBM PPC440X5 CPU Core User Manual

Preliminary

stswx

Store String Word Indexed
stswx RS, RA, RB
31
0 6
EA (RA|0) + (RB)
n XER[TBC]
r RS – 1
i 0
do while n > 0
if i = 0 then
r r + 1
if r = 32 then
r 0
MS(EA, 1) (GPR(r)
i i + 8
if i = 32 then
i 0
EA EA + 1
n n – 1
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
A byte count is contained in XER[TBC].
The contents of a series of consecutive GPRs (starting with register RS, continuing through GPR(31) and
wrapping to GPR(0) as necessary, and continuing to the final byte count) are stored, starting at the EA. The
bytes in each GPR are accessed starting with the most significant byte. The byte count determines the
number of transferred bytes.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Note
This instruction can be restarted, meaning that it could be interrupted after having already stored some of the
register values to memory, and then re-executed from the beginning (after returning from the interrupt), in
which case the registers which had already been stored prior to the interrupt will be stored a second time.
If XER[TBC] = 0, no GPRs are stored to memory, and stswx is treated as a no-op. Furthermore, if the EA is
such that a Data Storage, Data TLB Error, or Data Address Compare Debug exception occurs, stswx is
treated as a no-op and no interrupt occurs as a result of the exception.
instrset.fm.
September 12, 2002
RS RA
11
)
i:i+7
PPC440x5 CPU Core User's Manual
RB
16 21
stswx
Store String Word Indexed
661
31
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