IBM PPC440X5 CPU Core User Manual page 477

Preliminary
DAC 1 Write Debug Event
0 Event didn't occur
13 DAC1W
1 Event occurred
DAC 2 Read Debug Event
0 Event didn't occur
14 DAC2R
1 Event occurred
DAC 2 Write Debug Event
15 DAC2W 0 Event didn't occur
1 Event occurred
Return Debug Event
0 Event didn't occur
16 RET
1 Event occurred
17:29 Reserved
IAC 1/2 Auto-Toggle Status
0 Range is not reversed from value specified in
30 IAC12ATS
1 Range is reversed from value specified in
IAC 3/4 Auto-Toggle Status
0 Range is not reversed from value specified in
31 IAC34ATS
1 Range is reversed from value specified in
regsumm440core.fm.
September 12, 2002
DBCR1[IAC12M]
DBCR1[IAC12M]
DBCR1[IAC34M]
DBCR1[IAC34M]
DBSR (cont.)
Debug Status Register
PPC440x5 CPU Core User's Manual
Page 477 of 589