Ccr0; Figure 10-1. Core Configuration Register 0 (Ccr0) - IBM PPC440X5 CPU Core User Manual

CCR0

Core Configuration Register 0
PPC440x5 CPU Core User's Manual
CCR0
SPR 0x3B3 Supervisor R/W
See Core Configuration Register 0 (CCR0) on page 108.
PRE
0 1 2 3 4 5
CRPE
Figure 10-1. Core Configuration Register 0 (CCR0)
0 Reserved
Parity Recoverability Enable
0 Semi-recoverable parity mode enabled for data
1 PRE
1 Fully recoverable parity mode enabled for data
2:3 Reserved
Cache Read Parity Enable
0 Disable parity information reads
4 CRPE
1 Enable parity information reads
5:9 Reserved
Disable Store Gathering
0 Enabled; stores to contiguous addresses may be
10 DSTG
1 Disabled; all stores to memory will be performed
Disable APU Instruction Broadcast
0 Enabled.
11 DAPUIB
1 Disabled; instructions not broadcast to APU for
12:15 Reserved
Disable Trace Broadcast
0 Enabled.
16 DTB
1 Disabled; no trace information is broadcast.
Guaranteed Instruction Cache Block Touch
0
17 GICBT
1
Guaranteed Data Cache Block Touch
0
18 GDCBT
1
19:22 Reserved
Page 460 of 589
DSTG
9 10 11 12
DAPUIB
cache
cache
gathered into a single transfer
independently
decoding
icbt
may be abandoned without having filled
cache line if instruction pipeline stalls.
icbt
is guaranteed to fill cache line even if
instruction pipeline stalls.
dcbt/dcbtst
may be abandoned without
having filled cache line if load/store pipeline
stalls.
dcbt/dcbtst
are guaranteed to fill cache line
even if load/store pipeline stalls.
DTB GDCBT
15 16 17 18 19 22 23 24
GICBT
Must be set to 1 to guarantee full recoverability
from MMU and data cache parity errors.
When enabled, execution of icread, dcread, or
tlbre loads parity information into the ICDBTRH,
DCDBTRL, or target GPR, respectively.
See Store Gathering on page 119.
This mechanism is provided as a means of reduc-
ing power consumption when an auxilliary pro-
cessor is not attached and/or is not being used.
See Initialization on page 85.
This mechanism is provided as a means of reduc-
ing power consumption when instruction tracing is
not needed.
See Initialization on page 85.
See icbt Operation on page 111.
See Data Cache Control and Debug on
page 125.
Preliminary
ICSLC
27 28 29 30 31
FLSTA
regsumm440core.fm.
September 12, 2002
ICSLT