Operator Precedence; Register Usage; Table 9-3. Operator Precedence - IBM PPC440X5 CPU Core User Manual

Preliminary
instruction(EA)
leave
n
n
b
xx
–

9.3.1 Operator Precedence

Table 9-3 lists the pseudocode operators and their associativity in descending order of precedence:

Table 9-3. Operator Precedence

Operators
REG b , REG[FLD], function evaluation
n b
, – (unary minus)
+, –
u
u
=, , <, >, , >
<
,

9.4 Register Usage

Each instruction description lists the registers altered by the instruction. Some register changes are explicitly
detailed in the instruction description (for example, the target register of a load instruction). Some instructions
also change other registers, but the details of the changes are not included in the instruction descriptions.
instrset.fm.
September 12, 2002
An instruction operating on a data or instruction cache block associated
with an EA.
Leave innermost do loop or do loop specified in a leave statement.
A decimal number
The bit or bit value is replicated
b
Bit positions which are don't-cares.
Concatenation
Multiplication
Division yielding a quotient
Exclusive-OR (XOR) logical operator
Twos complement subtraction, unary minus
NOT logical operator
AND logical operator
OR logical operator
Associativity
Left to right
Right to left
Right to left
Left to right
Left to right
Left to right
Left to right
Left to right
Left to right
None
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