Andis - IBM PPC440X5 CPU Core User Manual

Preliminary

andis.

AND Immediate Shifted
andis. RA, RS, IM
29
0 6
(RA) (RS) (IM
The IM field is extended to 32 bits by concatenating 16 0-bits on its right. The contents of register RS are
ANDed with the extended IM field; the result is placed into register RA.
Registers Altered
• RA
• CR[CR0]
Programming Note
The andis. instruction can test whether any of the 16 most-significant bits in a GPR are 1-bits.
andis. is one of three instructions that implicitly update CR[CR0] without having an Rc field. The other
instructions are addic. and andi. .
instrset.fm.
September 12, 2002
RS RA
11
16
0)
PPC440x5 CPU Core User's Manual
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andis.
AND Immediate Shifted
IM
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