Tsr; Figure 10-48. Timer Status Register (Tsr) - IBM PPC440X5 CPU Core User Manual

TSR

Timer Status Register
PPC440x5 CPU Core User's Manual
TSR
SPR 0x150 Supervisor Read/Clear
See Timer Status Register (TSR) on page 216.
ENW WRS FIS
0 1 2 3 4 5 6
WIS
DIS

Figure 10-48. Timer Status Register (TSR)

Enable Next Watchdog Timer Exception
0 Action on next Watchdog Timer exception is to set
0 ENW TSR[ENW] = 1.
1 Action on next Watchdog Timer exception is governed
by TSR[WIS].
Watchdog Timer Interrupt Status
0 Watchdog Timer exception has not occurred.
1 WIS
1 Watchdog Timer exception has occurred.
Watchdog Timer Reset Status
00 No Watchdog Timer reset has occurred.
01 Core reset was forced by Watchdog Timer.
2:3 WRS
10 Chip reset was forced by Watchdog Timer.
11 System reset was forced by Watchdog Timer.
Decrementer Interrupt Status
0 Decrementer exception has not occurred.
4 DIS
1 Decrementer exception has occurred.
Fixed Interval Timer (FIT) Interrupt Status
0 Fixed Interval Timer exception has not occurred.
5 FIS
1 Fixed Interval Timer exception has occurred.
6:31 Reserved
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Preliminary
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regsumm440core.fm.
September 12, 2002