Exception Priorities For Trap Instructions; Exception Priorities For System Call Instruction - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
instructions that are implemented within the PPC440x5 core. This list also covers the defined 64-bit privileged
instructions, the tlbiva instruction, and the mfapidi instruction, all of which are not implemented by the
PPC440x5 core.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Program (Illegal Instruction exception)
Only applies to the defined 64-bit privileged instructions, the tlbiva instruction, and the mfapidi instruc-
tion.
5. Program (Privileged Instruction exception)
Does not apply to the defined 64-bit privileged instructions, the tlbiva instruction, nor the mfapidi instruc-
tion.
6. Debug (ICMP exception)
Does not apply to the defined 64-bit privileged instructions, the tlbiva instruction, nor the mfapidi instruc-
tion.

6.7.7 Exception Priorities for Trap Instructions

The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of a trap (tw, twi) instruction.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Debug (TRAP exception)
5. Program (Trap exception)
6. Debug (ICMP exception)

6.7.8 Exception Priorities for System Call Instruction

The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of a system call (sc) instruction.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. System Call (System Call exception)
5. Debug (ICMP exception)
Since the System Call exception does not suppress the execution of the sc instruction, but rather the excep-
tion occurs once the instruction has completed, it is possible for an sc instruction to cause both a System Call
exception and an ICMP Debug exception at the same time. In such a case, the associated interrupts will
occur in the order indicated in Interrupt Order on page 201.
Page 206 of 589
Preliminary
intrupts.fm.
September 12, 2002