IBM PPC440X5 CPU Core User Manual page 241

Preliminary
IAC 1 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
2:3 IAC1ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
IAC 2 User/Supervisor
00 Both
01 Reserved
4:5 IAC2US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
IAC 2 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
6:7 IAC2ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
IAC 1/2 Mode
00 Exact match
8:9 IAC12M
01 Reserved
10 Range inclusive
11 Range exclusive
10:14 Reserved
IAC 1/2 Auto-Toggle Enable
0 Disable IAC 1/2 auto-toggle
15 IAC12AT
1 Enable IAC 1/2 auto-toggle
IAC 3 User/Supervisor
00 Both
01 Reserved
16:17 IAC3US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
IAC 3 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
18:19 IAC3ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
IAC 4 User/Supervisor
00 Both
01 Reserved
20:21 IAC4US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
IAC 4 Effective/Real
00 Effective (MSR[IS] = don't care)
01 Reserved
22:23 IAC4ER
10 Virtual (MSR[IS] = 0)
11 Virtual (MSR[IS] = 1)
IAC 3/4 Mode
00 Exact match
24:25 IAC34M
01 Reserved
10 Range inclusive
11 Range exclusive
26:30 Reserved
debug.fm.
September 12, 2002
PPC440x5 CPU Core
Match if address[0:29] = IAC 1/2[0:29]; two inde-
pendent compares
Match if IAC1 address < IAC2
Match if address < IAC1 OR address
Match if address[0:29] = IAC 3/4[0:29]; two inde-
pendent compares
Match if IAC3 address < IAC4
Match if address < IAC3 OR address
User's Manual
IAC2
IAC4
Page 241 of 589