Instruction Address Compare Registers (Iac1-Iac4) - IBM PPC440X5 CPU Core User Manual

Preliminary
Interrupt Debug Event
0 Event didn't occur
6 IRPT
1 Event occurred
Trap Debug Event
0 Event didn't occur
7 TRAP
1 Event occurred
IAC 1 Debug Event
8 IAC1 0 Event didn't occur
1 Event occurred
IAC 2 Debug Event
0 Event didn't occur
9 IAC2
1 Event occurred
IAC 3 Debug Event
0 Event didn't occur
10 IAC3
1 Event occurred
IAC 4 Debug Event
11 IAC4 0 Event didn't occur
1 Event occurred
DAC 1 Read Debug Event
0 Event didn't occur
12 DAC1R
1 Event occurred
DAC 1 Write Debug Event
0 Event didn't occur
13 DAC1W
1 Event occurred
DAC 2 Read Debug Event
0 Event didn't occur
14 DAC2R
1 Event occurred
DAC 2 Write Debug Event
0 Event didn't occur
15 DAC2W
1 Event occurred
Return Debug Event
0 Event didn't occur
16 RET
1 Event occurred
17:29 Reserved
IAC 1/2 Auto-Toggle Status
0 Range is not reversed from value specified in
30 IAC12ATS
1 Range is reversed from value specified in
IAC 3/4 Auto-Toggle Status
0 Range is not reversed from value specified in
31 IAC34ATS
1 Range is reversed from value specified in
8.6.5 Instruction Address Compare Registers (IAC1–IAC4)
The four IAC registers specify the addresses upon which IAC debug events should occur. Each of the IAC
registers can be written from a GPR using
debug.fm.
September 12, 2002
DBCR1[IAC12M]
DBCR1[IAC12M]
DBCR1[IAC34M]
DBCR1[IAC34M]
mtspr , and can be read into a GPR using mfspr .
User's Manual
PPC440x5 CPU Core
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