Table A-1. Ppc440X5 Instruction Syntax Summary - IBM PPC440X5 CPU Core User Manual

Preliminary
Table A-1 summarizes the PPC440x5 instruction set, including required extended mnemonics. All
mnemonics are listed alphabetically, without regard to whether the mnemonic is realized in hardware or soft-
ware. When an instruction supports multiple hardware mnemonics (for example, b, ba, bl, bla are all forms of
b), the instruction is alphabetized under the root form. The hardware instructions are described in detail in
Chapter 9, "Instruction Set," which is also alphabetized under the root form. Section 9 also describes the
instruction operands and notation.
Programming Note: Bit 4 of the BO instruction field provides a hint about the most likely

Table A-1. PPC440x5 Instruction Syntax Summary

Mnemonic Operands
add
add.
RT, RA, RB
addo
addo.
addc
addc.
RT, RA, RB
addco
addco.
adde
adde.
RT, RA, RB
addeo
addeo.
addi
RT, RA, IM
addic
RT, RA, IM
addic.
RT, RA, IM
instalfa.fm.
September 12, 2002
outcome of a conditional branch. (See Branch Prediction on page 65 for
a detailed description of branch prediction.) Assemblers should set
BO = 0 unless a specific reason exists otherwise. In the BO field values
4
specified in Table A-1, BO
assembler must enable the programmer to specify branch prediction. To
do this, the assembler supports suffixes for the conditional branch
mnemonics:
+ Predict branch to be taken.
– Predict branch not to be taken.
For example, bc also could be coded as bc+ or bc–, and bne also could
be coded bne+ or bne–. These alternate codings set BO
requested prediction differs from the standard prediction. See Branch
Prediction on page 65 for more information.
Add (RA) to (RB).
Place result in RT.
Add (RA) to (RB).
Place result in RT.
Place carry-out in XER[CA].
Add XER[CA], (RA), (RB).
Place result in RT.
Place carry-out in XER[CA].
Add EXTS(IM) to (RA|0).
Place result in RT.
Add EXTS(IM) to (RA|0).
Place result in RT.
Place carry-out in XER[CA].
Add EXTS(IM) to (RA|0).
Place result in RT.
Place carry-out in XER[CA].
= 0 has always been assumed. The
4
Function
User's Manual
PPC440x5 CPU Core
= 1 only if the
4
Other Registers
Page
Changed
CR[CR0]
255
XER[SO, OV]
CR[CR0]
XER[SO, OV]
CR[CR0]
256
XER[SO, OV]
CR[CR0]
XER[SO, OV]
CR[CR0]
257
XER[SO, OV]
CR[CR0]
XER[SO, OV]
258
259
CR[CR0] 260
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