IBM PPC440X5 CPU Core User Manual page 166

User's Manual
PPC440x5 CPU Core
Critical Interrupt Enable
0 Critical Input and Watchdog Timer interrupts are
disabled.
14 CE
1 Critical Input and Watchdog Timer interrupts are
enabled.
15 Reserved
External Interrupt Enable
0 External Input, Decrementer, and Fixed Interval
Timer interrupts are disabled.
16 EE
1 External Input, Decrementer, and Fixed Interval
Timer interrupts are enabled.
Problem State
0 Supervisor state (privileged instructions can be
executed)
17 PR
1 Problem state (privileged instructions can not be
executed)
Floating Point Available
0 The processor cannot execute floating-point
instructions
18 FP
1 The processor can execute floating-point
instructions
Machine Check Enable
0 Machine Check interrupts are disabled
19 ME
1 Machine Check interrupts are enabled.
Floating-point exception mode 0
0 If MSR[FE1] = 0, ignore exceptions mode; if
MSR[FE1] = 1, imprecise nonrecoverable mode
20 FE0
1 If MSR[FE1] = 0, imprecise recoverable mode; if
MSR[FE1] = 1, precise mode
Debug Wait Enable
0 Disable debug wait mode.
21 DWE
1 Enable debug wait mode.
Debug interrupt Enable
0 Debug interrupts are disabled.
22 DE
1 Debug interrupts are enabled.
Floating-point exception mode 1
0 If MSR[FE0] = 0, ignore exceptions mode; if
MSR[FE0] = 1, imprecise recoverable mode
23 FE1
1 If MSR[FE0] = 0, imprecise non-recoverable
mode; if MSR[FE0] = 1, precise mode
24:25 Reserved
Instruction Address Space
0 All instruction storage accesses are directed to
address space 0 (TS = 0 in the relevant TLB
entry).
26 IS
1 All instruction storage accesses are directed to
address space 1 (TS = 1 in the relevant TLB
entry).
Data Address Space
0 All data storage accesses are directed to
address space 0 (TS = 0 in the relevant TLB
entry).
27 DS
1 All data storage accesses are directed to
address space 1 (TS = 1 in the relevant TLB
entry).
Page 166 of 589
Preliminary
intrupts.fm.
September 12, 2002