Divwu - IBM PPC440X5 CPU Core User Manual

divwu

Divide Word Unsigned
PPC440x5 CPU Core User's Manual
divwu
Divide Word Unsigned
divwu RT, RA, RB
divwu. RT, RA, RB
divwuo RT, RA, RB
divwuo. RT, RA, RB
31
0 6
(RT) (RA) (RB)
The contents of register RA are divided by the contents of register RB. The quotient is placed into register RT.
The dividend and the divisor are interpreted as unsigned integers. The quotient is the unique unsigned
integer that satisfies:
dividend = (quotient
If an attempt is made to perform (
the contents of CR[CR0]
CR[CR0] if Rc contains 1) to 1 if the OE field contains 1.
3
Registers Altered
• RT
• CR[CR0] if Rc contains 1
• XER[OV, SO] if OE contains 1
Programming Note
The 32-bit remainder can be calculated using the following sequence of instructions
divwu RT,RA,RB
mullw RT,RT,RB
subf RT,RT,RA
This sequence does not calculate the correct result if the divisor is 0.
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OE=0, Rc=0
OE=0, Rc=1
OE=1, Rc=0
OE=1, Rc=1
RT RA
11
divisor) + remainder
n 0), the contents of register RT are undefined; if the Rc also contains 1,
are also undefined. The invalid division operation also sets XER[OV, SO] (and
0:2
RB OE
16 21 22
# RT = quotient
# RT = quotient divisor
# RT = remainder
Preliminary
459 Rc
31
instrset.fm.
September 12, 2002