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S/D—Single-/Dual-Address Transfer
1 = The DMA channel runs single-address transfers from a peripheral to memory or
from memory to a peripheral. The destination holding register is not used for
these transfers because the data is transferred directly into the destination
location. The MC68340 on-chip peripherals do not support single-address
transfers.
0 = The DMA channel runs dual-address transfers.
STR—Start
This bit is cleared by a hardware/software reset, writing a logic zero, or setting one of
the following CSR bits: DONE, BES, BED, CONF, or BRKP. The STR bit cannot be set
when the CSR IRQ bit is set. The DMA channel cannot be started until the CSR DONE,
BES, BED, CONF, and BRKP bits are cleared.
Internal Request Mode:
1 = The DMA transfer starts as soon as this bit is set.
0 = The DMA transfer can be stopped by clearing this bit.
External Request Mode:
1 = Setting this bit allows the DMA to start the transfer when a DREQ input is
received from an external device.
0 = The DMA transfer can be stopped by clearing this bit.
If any fields in the CCR are modified while the channel is
active, that change is effective immediately. To avoid any
problems with changing the setup for the DMA channel, a zero
should be written to the STR bit in the CCR to halt the DMA
channel at the end of the current bus cycle.
6.7.4 Channel Status Register (CSR)
The CSR contains the channel status information. This register is accessible in either
supervisor or user space. The CSR can always be read or written to when the DMA
module is enabled (i.e., the STP bit in the MCR is cleared).
6-30
Freescale Semiconductor, Inc.
NOTE
CSR1, CSR2
7
6
5
4
IRQ
DONE
BES
BED
RESET
0
0
0
0
Supervisor/User
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
$78A, $7AA
3
2
1
0
CONF
BRKP
0
0
0
0
0
0
MOTOROLA
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