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MC68302 Applications
There is nothing to synchronize on the receive side. As soon as the ENR bit is set, the first
time slot for this SCC will begin the reception process. As with the NMSI mode, a word is
not written to the buffer until the 9th clock after the serial clock that clocked in the last bit of
this word (see D.8.7 Gating Clocks in NMSI Mode). Recall that clocks can only be counted
during time slots.
D.8.9 PCM Mode Final Thoughts
Since all synchronous protocols work with PCM mode, it is possible to use the regular BI-
SYNC mode to send syncs in the data stream, as described earlier.
When using totally transparent mode with PCM, both the NTSYN and EXSYN bits should
normally be set. The DIAG1-DIAG0 bits can be set for either normal mode or software op-
eration with no difference in behavior.
PCM mode does affect the SCCS register. In the SCCS register, the CD and CTS bits are
always zero when the ENR and ENT bits, respectively, are set. The ID bit is not valid in
transparent mode, regardless of the physical interface chosen.
Care should always be taken to avoid glitches or ringing on the L1CLK line. If a glitched or
ringing L1CLK line causes an extra clock to be inserted during a time slot, there is no way
to resynchronize the byte alignment in envelope mode until the ENT synchronization algo-
rithm described previously is followed. This potential problem does lead to one slight advan-
tage of the one-clock-prior method over the envelope sync. With the one-clock-prior method,
it is more likely that the glitched clock will only misalign the transfer/reception of a single byte
of data, rather than the whole data stream. (However, this cannot be guaranteed—predict-
ing device behavior out-of-spec is extremely difficult.)
D.8.10 Using Transparent Mode with IDL and GCI
Transparent mode can be freely used with the ISDN physical interfaces. Using transparent
mode with the ISDN interfaces is especially useful in the B-channels, since the D channel
LAPD protocol is typically supported with the SCC in HDLC mode. Transparent data may be
sent and received over the 64-kbps B1 channel, the 64-kbps B2 channel, a combined B1-
B2 channel with a 128-kbps bandwidth, or subportions of either the B1 or B2 channel or
both. (The desired subportions are defined in the SIMASK register.)
With the ISDN interfaces, as with the other types of interfaces, if the SCC is not transmitting
data, it will transmit $FFs. If the NTSYN and the EXSYN bits are set in the SCM, data will
be byte-aligned within the B1 or B2 channels. Thus, it will only be transmitted once the SCC
transmit FIFO is filled and the beginning of the B1 or B2 channel occurs.
A special case occurs when the B1 and B2 channels are combined into a single 128-kbps
channel. In this case, although data will only appear on byte boundaries, the transmit buff-
er's data could begin in either the B1 or B2 channels, depending on the timing involved. If
this is a problem, the following rule may be observed. If the ENT bit is set at a consistent
time during the GCI/IDL frame and if ready bit of the Tx BD is set at a consistent time relative
to the GCI/IDL frame (preferably before the ENT bit is set), a consistent starting point of byte
alignment (either B1 or B2) can be obtained. If data is then transmitted in a continuous
D-64
MC68302 USER'S MANUAL
MOTOROLA
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