Power Down; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
Follow these steps to reset the receive datapath in the GTH transceiver:
1.
2.
3.

Power Down

Functional Description

The GTH transceiver offers different levels of power control. Part of the power-down
functionality includes resetting certain logic within the GTH transceiver.

Ports and Attributes

Table 2-12
Table 2-12: Power-Down Ports
Port
POWERDOWN0
POWERDOWN1
POWERDOWN2
POWERDOWN3
RXPOWERDOWN0[1:0]
RXPOWERDOWN1[1:0]
RXPOWERDOWN2[1:0]
RXPOWERDOWN3[1:0]
TXPOWERDOWN0[1:0]
TXPOWERDOWN1[1:0]
TXPOWERDOWN2[1:0]
TXPOWERDOWN3[1:0]
66
Change RXPOWERDOWN<n>[1:0] to 2'b10 and wait for RXCTRLACK<n> to go
High. The CDR is disabled.
Change RXPOWERDOWN<n>[1:0] to 2'b00 and wait for RXCTRLACK<n> to go
High. The CDR is enabled.
Assert RXBUFRESET<n> for one RXUSERCLKIN clock cycle. The receiver is ready for
normal operation.
defines the power-down ports.
Dir Clock Domain
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
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Description
This control signal powers off the corresponding lane. It is
used to place individual lanes in a low power state. This
port is used on a per-lane basis even when multiple lanes
are configured as a single logical link.
This control signal requests the receiver power state:
00: Normal operation
10: Power-off receiver logic. The PLL continues to
operate in this state.
This port must always be set to 2'b10 during initialization
and when GTHRESET is asserted.
If the Quad is configured as a x4 link, only the port from
Lane 0 is valid.
This control signal requests the transmitter power state:
00: Normal operation
10: Power-off transmitter logic. The PLL continues to
operate in this state.
This port must always be set to 2'b10 during initialization
and when GTHRESET is asserted.
If the Quad is configured as a x4 link, only the port from
Lane 0 is valid.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010