Figure 2-11: Xc2Vpx20 Device Implementation; Figure 2-12: Xc2Vpx70 Device Implementation - Xilinx RocketIO X User Manual

Block Level Functions
be deterministic. Therefore, it is important that the interconnect of CHBONDO-to-
CHBONDI not contain any pipeline stages. The data must transfer from CHBONDO to
CHBONDI in one clock.
The data streams input to the channel bonded transceivers can be skewed in time from
each other. The maximum byte skew that the channel bond logic should allow is set by the
attribute MC_CHAN_BOND_LIMIT. During the channel bond operation, the slave
receives notification of the master's alignment code location via the CHBONDO bus. If a
slave detects the position of its alignment code to be outside the window of
CHAN_BOND_LIMIT from the master, then the slave does not perform the channel bond
and sets a channel bond error flag. If the channel bond is successful, the slave outputs its
skew relative to the master. The skew and channel bond error flag are available on the
RXBUFSTATUS bus.
For place and route, the transceiver has one restriction. This is required when channel
bonding is implemented. Because of the delay limitations on the CHBONDO to CHBONDI
ports, linking of the Master to a Slave_1_hop must run either in the X or Y direction, but not
both.
In
navigate to the other slave (a Slave_2_hops), both X and Y displacement is needed. This
slave needs one level of daisy-chaining, which is the basis of the Slave_2_hops setting.
Figure 2-11
and XC2VPX70 devices, which (optionally) contain more transceivers (20) per chip. To
ensure the timing is met on the link between the CHBONDO and CHBONDI ports, a
constraint must be added to check the time delay.
CHBONDI CHBONDO
CHBONDO CHBONDI
SLAVE_1_HOP
SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
CHBONDI CHBONDO
CHBONDO CHBONDI
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Figure 2-11, the two Slave_1_hops are linked to the master in only one direction. To
and Figure 2-12
SLAVE_1_HOP MASTER
CHBONDI CHBONDO
CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_1_HOP

Figure 2-11: XC2VPX20 Device Implementation

SLAVE_1_HOP SLAVE_1_HOP MASTER
CHBONDI CHBONDO CHBONDI CHBONDO
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_1_HOP

Figure 2-12: XC2VPX70 Device Implementation

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show the channel bonding mode and linking for an XC2VPX20
SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
Top of device
Bottom of device
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS
SLAVE_1_HOP SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS
SLAVE_1_HOP
SLAVE_2_HOPS
UG035_ch2_10_091603
SLAVE_1_HOP SLAVE_1_HOP
CHBONDI CHBONDO CHBONDI CHBONDO
Top of device
Bottom of device
CHBONDO CHBONDI CHBONDO CHBONDI
SLAVE_2_HOPS SLAVE_2_HOPS
UG035_ch2_11_051904
R
SLAVE_1_HOP
CHBONDI CHBONDO
CHBONDO CHBONDI
SLAVE_2_HOPS
67