Ports And Attributes; Clk_Correct_Use; Rx_Buffer_Use - Xilinx RocketIO User Manual

R
CLK_COR_REPEAT_WAIT is 0, the transceiver can also skip four consecutive removable byte
sequences in one step, to further empty the buffer when necessary.
These operations require the clock correction logic to recognize a byte sequence that can be freely
repeated or omitted in the incoming data stream. This sequence is generally an IDLE sequence, or
other sequence comprised of special values that occur in the gaps separating packets of meaningful
data. These gaps are required to occur sufficiently often to facilitate the timely execution of clock
correction.
The clock correction logic has the ability to remove up to four IDLE sequences during a clock
correction. How many IDLEs are removed depends on several factors, including how many IDLEs
are received and whether CLK_COR_KEEP_IDLE is TRUE or FALSE. For example, if three
IDLEs are received and CLK_COR_KEEP_IDLE is set to TRUE, at least one IDLE sequence must
remain after clock correction has been completed. This limits the clock correction logic to remove
only two of the three IDLE sequences. If CLK_COR_KEEP_IDLE is FALSE, then all three IDLEs
can be removed.
Table 2-14
stability of REFCLK, and the number of bytes allowed between clock correction sequences.
Table 2-14: Data Bytes Allowed Between Clock Corrections as a Function of
REFCLK Stability and IDLE Sequences Removed

Ports and Attributes

CLK_CORRECT_USE

This attribute controls whether the PCS will repeat/skip the clock correction sequences (CCS) from
the elastic buffer to compensate for differences between the clock recovered from serial data and the
reference clocks. When this attribute is set to TRUE, the clock correction is enabled. If set to
FALSE, clock correction is disabled. When clock correction is disabled, RXRECCLK must drive
the receive logic in the fabric. Otherwise, the elastic buffer may over/underflow.
Clock correction may be used with other encoding protocols, but they must have a 10-bit alignment
scheme. This is required so the comma detection logic can properly align the data in the elastic
buffer, allowing the clock correction logic to properly read out data to the FPGA fabric.

RX_BUFFER_USE

The RX_BUFFER_USE attribute controls if the elastic buffer is bypassed or not. Most applications
use this buffer for clock correction and channel bonding. (See
Alignment)," page
74
illustrates the relationship between the number of IDLE sequences removed, the inherent
Bytes Allowed Between Clock Correction Sequences
REFCLK Remove 1 IDLE
Stability Sequence:
100 ppm 5,000
50 ppm 10,000
20 ppm 25,000
Notes:
1. All numbers are approximate.
2. IDLE = the defined clock correction sequence.
79.) It is recommended that this attribute always be set to TRUE, since this
Chapter 2: Digital Design Considerations
(2)
Remove 2 IDLE
Sequences:
10,000
20,000
50,000
www.xilinx.com
1-800-255-7778
(1)
Remove 3 IDLE Remove 4 IDLE
Sequences: Sequences:
15,000 20,000
30,000 40,000
75,000 100,000
"Channel Bonding (Channel
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004