Vhdl - Xilinx RocketIO User Manual

Other Important Design Notes

VHDL

RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
// Here, you could add code to use ENPCOMMAALIGN and
// ENMCOMMAALIGN to enable a move back into the byte_sync=0 state.
always @ ( posedge usrclk2 or posedge rxreset )
begin
if ( rxreset )
begin
rxdata_reg <= 16'h0000;
aligned_data
rxisk_reg
aligned_rxisk
byte_sync
end
else
begin
rxdata_reg[15:0] <= rxdata[15:0];
rxisk_reg[1:0]
if ( rxchariscomma3 )
begin
aligned_data[31:0] <= rxdata[31:0];
aligned_rxisk[3:0]
byte_sync
end
else
if ( rxchariscomma1 | byte_sync )
begin
aligned_data[31:0] <= { rxdata_reg[15:0], rxdata[31:16]
};
aligned_rxisk[3:0]
byte_sync
end
else
begin
aligned_data[31:0] <= rxdata[31:0];
aligned_rxisk <= rxisk;
end
end
end
endmodule // align_comma_32
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<= 32'h0000_0000;
<= 2'b00;
<= 4'b0000;
<= 1'b0;
<= rxisk[1:0];
<= rxisk[3:0];
<= 1'b0;
<= { rxisk_reg[1:0], rxisk[3:2] };
<= 1'b1;
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XILINX EXPRESSLY DISCLAIMS ANY
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