Differential Trace Design; Figure 4-10: Single-Ended Trace Geometry - Xilinx RocketIO User Manual

R
impedance traces with a corresponding impedance should be used to connect the
RocketIO transceiver to other compatible transceivers. In chip-to-chip PCB applications,
50Ω termination and 100Ω differential transmission lines are recommended.
When routing a differential pair, the complementary traces must be matched in length to as
close a tolerance as is feasible. Length mismatches produce common mode noise and
radiation. Severe length mismatches produce jitter and unpredictable timing problems at
the receiver. Matching the differential traces to within 50 mils (1.27 mm) produces a robust
design. Since signals propagate in FR4 PCB traces at approximately 180 ps per inch, a
difference of 50 mils produces a timing skew of roughly 9 ps. Use SI CAD tools to confirm
these assumptions on specific board designs.
All signal traces must have an intact reference plane beneath them. Stripline and
microstrip geometries may be used. The reference plane should extend no less than five
trace widths to either side of the trace to ensure predictable transmission line behavior.
Routing of a differential pair is optimally done in a point-to-point fashion, ideally
remaining on the same PCB routing layer. As vias represent an impedance discontinuity,
layer-to-layer changes should be avoided wherever possible. It is acceptable to traverse the
PCB stackup to reach the transmitter and receiver package pins. If serial traces must
change layers, care must be taken to ensure an intact current return path. For this reason,
routing of high-speed serial traces should be on signal layers that share a reference plane.
If the signal layers do not share a reference plane, a capacitor of value 0.01 µF should be
connected across the two reference layers close to the vias where the signals change layers.
If both of the reference layers are DC coupled (if they are both ground), they can be
connected with vias close to where the signals change layers.
To control crosstalk, serial differential traces should be spaced at least five trace separation
widths from all other PCB routes, including other serial pairs. A larger spacing is required
if the other PCB routes carry especially noisy signals, such as TTL and other similarly noisy
standards.
The RocketIO transceiver is designed to function at 3.125 Gb/s through 20 inches of FR4
with two high-bandwidth connectors. Longer trace lengths require either a low-loss
dielectric or considerably wider serial traces.

Differential Trace Design

The characteristic impedance of a pair of differential traces depends not only on the
individual trace dimensions, but also on the spacing between them. The RocketIO
transceivers require either a 100Ω or 150Ω differential trace impedance (depending on
whether the 50Ω or 75Ω termination option is selected). To achieve this differential
impedance requirement, the characteristic impedance of each individual trace must be
slightly higher than half of the target differential impedance. A field solver should be used
to determine the exact trace geometry suited to the specific application
task should not be left up to the PCB vendor.
Differential impedance of traces on the finished PCB should be verified with Time Domain
Reflectometry (TDR) measurements.
92
W
Trace
E = 4.3 H
r
Reference Plane

Figure 4-10: Single-Ended Trace Geometry

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Chapter 4: Analog Design Considerations
W = 7.9 mil (0.201 mm)
H = 5.0 mil (0.127 mm)
Z = 50Ω
0
Dielectric
UG024_21_041902
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
(Figure 4-10). This