Ports And Attributes; Tx_Crc_Use; Rx_Crc_Use; Crc_Format - Xilinx RocketIO User Manual

CRC (Cyclic Redundancy Check)
Table 2-20: Effects of CRC on Transceiver Latency
CRC Enabled
Notes:
1. See Table 2-6 and Table 2-7
2. This maximum may occur when certain conditions are present, and clock correction and channel bonding are
enabled. If these functions are both disabled, the maximum will be near the typical values.
3. To further reduce receive-side latency, refer to

Ports and Attributes

TX_CRC_USE,

RX_CRC_USE

These two attributes control whether the MGT CRC circuitry is enabled or bypassed. When set to
TRUE, CRC is enabled. When set to FALSE, CRC is bypassed and must be implemented in the
FPGA fabric.

CRC_FORMAT

There are four possible CRC modes: USER_MODE, FIBRE_CHAN, ETHERNET, and
INFINIBAND. This attribute is modifiable only for the GT_XAUI and GT_CUSTOM primitives.
Each mode has a Start of Packet (SOP) and End of Packet (EOP) setting to determine where to start
and end the CRC monitoring. USER_MODE allows the user to define the SOP and EOP by setting
the CRC_START_OF_PKT and CRC_END_OF_PKT to one of the valid K-characters
page
attributes are set to TRUE, CRC is used.
The four modes are defined in the subsections following.
USER_MODE
USER_MODE is the simplest CRC methodology. The CRC checks for the SOP and EOP, calculates
CRC on the data, and leaves the four remainders directly before the EOP. The CRC form for the
user-defined mode is shown in
and RXCRCERR are asserted High with respect to the incoming data.
To check the CRC error detection logic in a testing mode such as serial loopback, a CRC error can
be forced by setting TXFORCECRCERR to High, which incorporates an error into the transmitted
data. When that data is received, it appears "corrupted," and the receiver signals an error by
asserting RXCRCERR High at the same time RXCHECKINGCRC goes High. User logic
determines the procedure that is invoked when a CRC error occurs.
FIBRE_CHAN
The FIBRE_CHAN CRC is similar to USER_MODE CRC
FIBRE_CHAN, SOP and EOP are predefined protocol delimiters. Unlike USER_MODE,
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
TXDATA to TXP and TXN
in TXUSRCLK Cycles
Typical Maximum
14 17
for all MGT block latency parameters.
Appendix C, "Related Online Documents."
141). The CRC is controlled by RX_CRC_USE and TX_CRC_USE. Whenever these
Note:
Data length must be greater than 20 bytes for USER_MODE CRC generation. For CRC
to operate correctly, at least four gap bytes are required between EOP of one packet and SOP of
the next packet. The gap may contain clock correction sequences, provided that at least 4 bytes
of gap remain after all clock corrections.
(1)
RXP and RXN to RXDATA
in RXUSRCLK Cycles
Typical
25
Figure 2-24, along with the timing for when RXCHECKINGCRC
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(3)
Maximum
(2)
42
(Figure 2-24), with one exception: In
R
(Table B-2,
85