Figure 3-13: Brefclk 2:1:2; Figure 3-14: Txoutclk 2:1:2 - Xilinx RocketIO X User Manual
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Also See for RocketIO X:
- User manual (152 pages) ,
- User manual (156 pages) ,
- User manual (124 pages)
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Clock Domain Architecture
BREFCLK
USRCLK
USRCLK2 and
User Logic
TXOUTCLK
USRCLK
USRCLK2 and
User Logic
Note:
in the FPGA fabric on the receive side. This can be used to avoid clock correction schemes. The TX
can have any of the other 1:2 use models. Also, the waveform only indicates the receive clocks.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Figure 3-13: BREFCLK 2:1:2
Figure 3-14: TXOUTCLK 2:1:2
Figure 3-15
shows the RocketIO X transceiver instantiated using the recovered clock to clock
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1-800-255-7778
DCM
CLKIN
CLKDV
CLK180
CLK0
CLKFB
DV ratio = 2
User
TX & RX
Logic
CLK0 and local inversion
at USRCLK2 and user
logic can be implemented
to save BUFG resources
DCM
CLKIN
CLKDV
CLK180
CLK0
CLKFB
DV ratio = 2
User
TX & RX
Logic
local inversion of CLK0 at
USRCLK2 and User Logic
can be implemented to
reduce BUFG utilization
R
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
BUFG
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
UG035_CH3_26_060304
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
BUFG
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
UG035_CH3_27_060304
81
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