Clock Correction Sequences - Xilinx RocketIO X User Manual

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CLK_COR_MIN_LAT. This is also true for a correction to the latency due to a
CLK_COR_MIN_LAT violation; the resulting latency after the correction is greater than
CLK_COR_MAX_LAT.

Clock Correction Sequences

Searching within the bitstream for an idle is the core function of the clock correction circuit.
The detection of idles starts the correction procedure.
Idles the clock correction circuit should detect are specified by the lower 10 bits of the
attributes:
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The 11th bit of each clock correction sequence attribute determines either an 8- or 10-bit
compare.
Detection of the clock correction sequence in the bitstream is specified by eight words
consisting of 10 bits each. Clock correction sequences can have lengths of 1, 2, 3, 4 or 8
bytes.
When the length specified by the user is between 1 and 4, CLK_COR_SEQ_1_* holds the
first pattern to be searched for. CLK_COR_SEQ_1_1 is the least significant byte, which is
transmitted first from the transmitter and detected first in the receiver. If
CLK_COR_SEQ_2_USE is asserted High when the length is between 1 and 4, the sequence
specified by CLK_COR_SEQ_2_* is specified as a second pattern to match. In that case, the
pattern specified by sequence 1 or sequence 2 matches as a clock correction sequence.
Note:
bytes.
When the length specified by the user is eight, CLK_COR_SEQ_1_* holds the first four
bytes, while CLK_COR_SEQ_2_* holds the last four bytes. CLK_COR_SEQ_1_1 is the least
significant byte, which is transmitted first from the transmitter and detected first in the
receiver. CLK_COR__SEQ_2_USE must be asserted High.
The clock correction sequence is a special sequence to accommodate frequency differences
between the received data (as reflected in RXRECCLK) and RXUSRCLK. Most of the
primitives have these defaulted to the respective protocols. Only the GT_CUSTOM allows
this sequence to be set to any specific protocol. The sequence contains 11 bits including the
10 bits of serial data. The 11th bit has two different formats. The typical usage is:
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CLK_COR_SEQ_1_1
CLK_COR_SEQ_1_2
CLK_COR_SEQ_1_3
CLK_COR_SEQ_1_4
CLK_COR_SEQ_2_1
CLK_COR_SEQ_2_2
CLK_COR_SEQ_2_3
CLK_COR_SEQ_2_4
The CLK_COR_SEQ_MASK must have the bits set to a logic 1 mask off the 2 or 3 unused
0, disparity error required, char is K, 8-bit data value (after 8B/10B decoding, depends
on CLK_COR_8B10B_DE)
0, 10-bit data value (without 8B/10B decoding, depends on CLK_COR_8B10B_DE)
1, xx, sync character (with 64B/66B encoding
1, xx, 8-bit data value
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Chapter 2: Digital Design Considerations
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004