Txbuswid; Txloopfilterc[1:0]; Txloopfilterr[1:0]; Table C-7: Txbuswid Definition - Xilinx RocketIO X User Manual

Register Definition
Table C-6: TXOUTCLK Divider Ratio Definition (Continued)

TXBUSWID

TXBUSWID selects between wide and narrow internal parallel transmit data bus. The
default is 1 (Wide). The bus width settings are defined as follows:

Table C-7: TXBUSWID Definition

TXLOOPFILTERC[1:0]

TXLOOPFILTERC[1:0] selects the transmit PLL filter capacitor setting. The default is
primitive dependent. The loop filter capacitor selection is as follows:

Table C-8: TXLOOPFILTERC[1:0] Definition

TXLOOPFILTERR[1:0]

TXLOOPFILTERR[1:0] selects the transmit PLL filter resistor setting. The default is
primitive dependent. The loop filter resistor selection is as follows:

Table C-9: TXLOOPFILTERR[1:0] Definition

RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
TXDIVRATIO[9:6]
1010
1011
1100
1101
1110
1111
TXBUSWID
0
1
TXLOOPFILTERC[1:0]
00
01
10
11
TXLOOPFILTERR[1:0]
00
01
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Divider
÷ 20
Reserved
Reserved
Reserved
Reserved
Reserved
TX Parallel Bus Width
16/20 bit
32/40 bit (default)
TX Filter Capacitor
15 pF
30 pF
45 pF
60 pF
TX Filter Resistor
12 kΩ
6 kΩ
R
151