Figure 3-15: Rxrecclk 2:1:2 - Xilinx RocketIO X User Manual

R
RXRECCLK*
USRCLK
USRCLK2 and
User Logic
*RXRECCLK should only drive the receive clocks
82
DV ratio = 2
local inversion of CLK0 at
USRCLK2 and User Logic
can be implemented to
reduce BUFG utilization

Figure 3-15: RXRECCLK 2:1:2

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Chapter 3: Clocking and Clock Domains
DCM
CLKIN
CLKDV
CLK180
CLK0
CLKFB
BUFG
User
TX & RX
Logic
UG035_CH3_28_060304
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK