Clk_Cor_Seq_; Clk_Cor_Keep_Idle Clk_Cor_Repeat_Wait - Xilinx RocketIO User Manual

Clock Recovery
buffer allows a way to cross the clock domains of RXRECCLK and the fabric
RXUSRCLK/RXUSRCLK2.

CLK_COR_SEQ_ * _ *

To accommodate many different protocols, the MGT features programmability that allows it to
detect a 1-, 2-, or 4-byte clock correction sequence (CCS), such as may be used in Gigabit Ethernet
(2-byte) or Fibre Channel (4-byte). The attributes CLK_COR_SEQ_*_* and
CLK_COR_SEQ_LEN (below) define the CCS that the PCS recognizes. Both SEQ_1 and SEQ_2
can be used at the same time if multiple CCSs are required. As shown in
CCS has two possible modes, one for when 8B/10B encoding is used, the other for when 8B/10B
encoding is bypassed. The most significant bit of the CCS determines whether it is applicable to an
8-bit (encoded) or a 10-bit (unencoded) sequence.
These sequences require that the encoding scheme allows the comma detection and alignment
circuitry to properly align data in the elastic buffer. (See "CLK_CORRECT_USE", above). The bit
definitions are the same as shown earlier in the Vitesse channel-bonding example. (See
Vitesse Channel Bonding
Table 2-15: Clock Correction Sequence / Data Correlation for 16-Bit Data Port
CLK_COR_SEQ_LEN
To define the CCS length, this attribute takes the integer value 1, 2, 3, or 4.
sequences are used for the four possible settings of CLK_COR_SEQ_LEN.
Table 2-16: Applicable Clock Correction Sequences
CLK_COR_INSERT_IDLE_FLAG,
CLK_COR_KEEP_IDLE,
CLK_COR_REPEAT_WAIT
These attributes help control how clock correction is implemented.
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
Sequence.")
Attribute Settings
CLK_COR_SEQ 8-Bit Data Mode
CLK_COR_SEQ_1_1
00110111100
CLK_COR_SEQ_1_2
00010010101
CLK_COR_SEQ_1_3
00010110101
CLK_COR_SEQ_1_4
00010110101
CLK_COR_SEQ_LEN
1
2
3
4
Notes:
1. Applicable only if CLK_COR_SEQ_2_USE is set to TRUE.
10-Bit Data Mode
(8B/10B Bypass)
10011111010
11010100010
11010101010
11010101010
CLK_COR_SEQ_1
That Are Applicable
1_1
1_1, 1_2
1_1, 1_2, 1_3
1_1, 1_2, 1_3. 1_4
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Table 2-15, the example
"Receiving
TXDATA
Character CHARISK
K28.5 1
D21.4 0
D21.5 0
D21.5 0
Table 2-16 shows which
CLK_COR_SEQ_2
That Are Applicable
2_1
2_1, 2_2
2_1, 2_2, 2_3
2_1, 2_2, 2_3, 2_4
R
(hex)
ΒΧ
95
Β5
Β5
(1)
75