Clk_Cor_Insert_Idle_Flag; Clk_Cor_Keep_Idle; Clk_Cor_Repeat_Wait; Synchronization Logic - Xilinx RocketIO User Manual

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CLK_COR_INSERT_IDLE_FLAG is a TRUE/FALSE attribute that defines the output of the
RXRUNDISP port. When set to TRUE, RXRUNDISP is raised for the first byte of each inserted
(repeated) clock correction sequence (8B/10B decoding enabled). When set to FALSE (default),
RXRUNDISP denotes the running disparity of RXDATA (8B/10B decoding enabled).
CLK_COR_KEEP_IDLE is a TRUE/FALSE attribute that controls whether or not the final byte
stream must retain at least one clock correction sequence. When set to FALSE (default), the clock
correction logic is allowed to remove all clock correction sequences if needed to recenter the elastic
buffer. When set to TRUE, it forces the clock correction logic to retain at least one clock correction
sequence per continuous stream of clock correction sequences.
Example: Elastic buffer is 75% full and clock correction is needed. (IDLE is the defined clock
correction sequence.)
Data stream written into elastic buffer:
Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = FALSE)
Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = TRUE)
CLK_COR_REPEAT_WAIT is an integer attribute (0-31) that controls frequency of repetition of
clock correction operations. This attribute specifies the minimum number of RXUSRCLK cycles
without clock correction that must occur between successive clock corrections. For example, if this
attribute is 3, then at least three RXUSRCLK cycles without clock correction must occur before
another clock correction sequence can occur. If this attribute is 0, no limit is placed on how
frequently clock correction can occur.
Example: Elastic buffer is 25% full, clock correction is needed, and one sequence is repeated per
clock correction. (IDLE is the defined clock correction sequence.)
Data stream written into elastic buffer:
Data stream read out of elastic buffer (CLK_COR_REPEAT_WAIT = 0):
Data stream read out of elastic buffer (CLK_COR_REPEAT_WAIT = 1):
The percent that the buffer is full, together with the value of CLK_COR_REPEAT_WAIT,
determines how many times the clock correction sequence is repeated during each clock correction.

Synchronization Logic

Overview

For some applications, it is beneficial to know if incoming data is valid or not, and if the MGT is
synchronized on the data. For applications using the 8B/10B encoding scheme, the
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D0 IDLE IDLE
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D0 IDLE D1
D0 IDLE IDLE
D0 IDLE IDLE
D0 IDLE IDLE
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Chapter 2: Digital Design Considerations
IDLE IDLE D1
D2
IDLE D1 D2
IDLE IDLE IDLE
IDLE IDLE IDLE
RocketIO™ Transceiver User Guide
D2
IDLE D1 D2
D1 D2
UG024 (v2.3.2) June 24, 2004