Brefclk; Figure 3-4: Refclk/Brefclk Selection Logic - Xilinx RocketIO User Manual

R

BREFCLK

At speeds of 2.5 Gb/s or greater, the REFCLK configuration introduces more than the
maximum allowable jitter to the RocketIO transceiver. For these higher speeds, the
BREFCLK configuration is required. The BREFCLK configuration uses dedicated routing
resources that reduce jitter.
BREFCLK must enter the FPGA through dedicated clock I/O. This BREFCLK can connect
to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of
USRCLKs. If all the transceivers on a Virtex-II Pro FPGA are to be used, two BREFCLKs
must be created, one for the top of the chip and one for the bottom.
These dedicated clocks use the same clock inputs for all packages: .
Figure 3-4
and REF_CLK_V_SEL.
50
BREFCLK
Top
BREFCLK2
BREFCLK
Bottom
BREFCLK2
shows how REFCLK and BREFCLK are selected through use of REFCLKSEL
refclk
0
1.5V
refclk2
1
REFCLKSEL
brefclk
0
2.5V
brefclk2
1

Figure 3-4: REFCLK/BREFCLK Selection Logic

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Chapter 3: Digital Design Considerations
P GCLK4S
N GCLK5P
P GCLK2S
N GCLK3P
P GCLK6P
N GCLK7S
P GCLK0P
N GCLK1S
REF_CLK_V_SEL
0
refclk_out
to PCS and PMA
1
ug024_35_091802
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide