Clock Ports; Table 3-1: Clock Ports - Xilinx RocketIO X User Manual

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Clock Ports

Table 3-1: Clock Ports

Clock
BREFCLKNIN
BREFCLKPIN
REFCLK
REFCLK2
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
RXRECCLK Output
TXOUTCLK Output
REFCLKBSEL
REFCLKSEL
74
I/Os
Input Reference clock used for generating high-frequency timing in the TX and RX
PLLs. The multiplication ratio for parallel-to-serial conversion is
mode/protocol dependent.
Input Reference clock used for generating high-frequency timing in the TX and RX
PLLs. The multiplication ratio for parallel-to-serial conversion is
mode/protocol dependent. This clock is a higher jitter clock. If used,
performance based on data sheet numbers will not be met.
Input Reference clock used for generating high-frequency timing in the TX and RX
PLLs. The multiplication ratio for parallel-to-serial conversion is
mode/protocol dependent. This clock is a higher jitter clock. If used,
performance based on data sheet numbers will not be met.
Input Clock from FPGA used for reading the RX Elastic Buffer. Clock signals
CHBONDI and CHBONDO into and out of the transceiver. This clock is
typically the same as TXUSRCLK, but if RXRECCLK is used to source a DCM,
this clock can be frequency locked to the recovered clock.
Input Clock from FPGA used to clock RX data and status between the transceiver and
FPGA fabric. The relationship between RXUSRCLK2 and RXUSRCLK depends
on the width of the receiver data path. RXUSRCLK2 is typically the same as
TXUSRCLK2, but if RXRECCLK is used to source a DCM, this clock can be
frequency locked to the recovered clock.
Input Clock from FPGA used for writing the TX Buffer. This clock must be frequency
locked to TXOUTCLK for proper operation.
Input Clock from FPGA used to clock TX data and status between the transceiver and
FPGA fabric. The relationship between TXUSRCLK2 and TXUSRCLK depends
on the width of the transmission data path.
Recovered clock from serial data stream. This clock is scaled based upon the
specific mode/protocol.
Scaled transmit clock generated within TX clock management unit. This clock
is scaled based upon the specific mode/protocol.
Input Selects between REFCLK/REFCLK2 and BREFCLK. 0 selects
REFCLK/REFCLK2 (based on REFCLKSEL); 1 selects BREFCLK.
Input Selects which reference clock is used (when REFCLKBSEL=0). 0 selects
REFCLK; 1 selects REFCLK2.
Chapter 3: Clocking and Clock Domains
Description
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RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004