Schedule Of Figures - Xilinx RocketIO User Manual

Figures
Chapter 1: Introduction
Chapter 2: RocketIO Transceiver Overview
Figure 2-1: RocketIO Transceiver Block Diagram ................................................................. 16
Figure 2-2: Clock Correction in Receiver ................................................................................. 21
Figure 2-3: Channel Bonding (Alignment) .............................................................................. 22
Chapter 3: Digital Design Considerations
Figure 3-1: Two-Byte Clock ........................................................................................................ 40
Figure 3-2: Four-Byte Clock ........................................................................................................ 43
Figure 3-3: One-Byte Clock......................................................................................................... 46
Figure 3-4: REFCLK/BREFCLK Selection Logic ..................................................................... 50
Figure 3-5: One-Byte Data Path Clocks, SERDES_10B = TRUE.......................................... 52
Figure 3-6: Two-Byte Data Path Clocks, SERDES_10B = TRUE ......................................... 52
Figure 3-7: Four-Byte Data Path Clocks, SERDES_10B = TRUE ......................................... 52
Figure 3-8: Multiplexed REFCLK .............................................................................................. 53
Figure 3-9: 8B/10B Data Flow ..................................................................................................... 58
Figure 3-10: 10-Bit TX Data Map with 8B/10B Bypassed ...................................................... 59
Figure 3-11: 10-Bit RX Data Map with 8B/10B Bypassed ...................................................... 59
Figure 3-12: 8B/10B Parallel to Serial Conversion.................................................................. 69
Figure 3-13: 4-Byte Serial Structure........................................................................................... 70
Figure 3-14: CRC Packet Format ................................................................................................ 71
Figure 3-15: USER_MODE / FIBRE_CHANNEL Mode ........................................................ 72
Figure 3-16: Ethernet Mode ........................................................................................................ 72
Figure 3-17: Infiniband Mode .................................................................................................... 73
Figure 3-18: Local Route Header................................................................................................ 73
Figure 3-19: RXDATA Aligned Correctly ................................................................................ 75
Figure 3-20: Realignment of RXDATA..................................................................................... 76
Chapter 4: Analog Design Considerations
Figure 4-1: Differential Amplifier............................................................................................. 83
Figure 4-2: Alternating K28.5+ with No Pre-Emphasis ......................................................... 85
Figure 4-3: K28.5+ with Pre-Emphasis...................................................................................... 85
Figure 4-5: Eye Diagram, 33% Pre-Emphasis .......................................................................... 86
Figure 4-4: Eye Diagram, 10% Pre-Emphasis .......................................................................... 86
Figure 4-6: Power Supply Circuit Using LT1963 Regulator ................................................. 89
Figure 4-7: Power Filtering Network for One Transceiver................................................... 90
Figure 4-8: Example Power Filtering PCB Layout for Four MGTs, Top Layer................. 91
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
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