Multiplexed Clocking Scheme With Dcm; Multiplexed Clocking Scheme Without Dcm - Xilinx RocketIO User Manual

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Multiplexed Clocking Scheme with DCM

Following configuration of the FPGA, some applications might need to change the frequency of its
REFCLK depending on the protocol used.
reference clocks connected to two different DCMs. The clocks are then multiplexed before input
into the RocketIO transceiver.
User logic can be designed to determine during auto negotiation if the reference clock used for the
transceiver is incorrect. If so, the transceiver must then be reset and another reference clock selected.

Multiplexed Clocking Scheme without DCM

As with
removed if TXDATA and RXDATA are not clocked off the FPGA. (See
transceiver must still be reset when clocks are switched.
56
IBUFGDS
REFCLK_P
REFCLK_N
REFCLK2_P
REFCLK2_N
REFCLKSEL
Figure 2-9: Multiplexed REFCLK with DCM
"Example 1b: Two-Byte Clock without
IBUFGDS
REFCLK_P
REFCLK_N
REFCLK2_P
REFCLK2_N
REFCLKSEL
Figure 2-10: Multiplexed REFCLK without DCM
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Chapter 2: Digital Design Considerations
Figure 2-9 shows how the design can use two different
DCM
CLKIN
CLKFB
RST
CLK0
DCM
CLKIN
0
CLKFB
RST
1
CLK0
BUFGMUX
DCM", the DCMs shown in
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
Use of 2 DCMs is required
to maintain correct
IBUFG/DCM/BUFGMUX topology
for clock skew compensation
UG024_05a_112202
Figure 2-9
Figure 2-10.) However, the
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
0
RXUSRCLK
1
BUFGMUX
UG024_05b_021503
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
may be