Other Important Design Notes; Powering The Rocketio Transceivers; The Powerdown Port - Xilinx RocketIO User Manual

Other Important Design Notes

Other Important Design Notes

Powering the RocketIO Transceivers

IMPORTANT! All RocketIO transceivers in the FPGA, whether instantiated in the design
or not, must be connected to power and ground. Unused transceivers may be powered by
any 2.5 V source, and passive filtering is not required. Refer to
page
The maximum power consumption per port is 350 mW at 3.125 Gb/s operation.

The POWERDOWN Port

POWERDOWN is a single-bit primitive port (see
off the transceiver in case it is not needed for the design, or will not be transmitting or
receiving for a long period of time. When POWERDOWN is asserted, the transceiver does
not use any power. The clocks are disabled and do not propagate through the core. The
3-state TXP and TXN pins are set to high-Z, while the outputs to the fabric are frozen but
not set to high-Z.
Any given transceiver that is not instantiated in the design will automatically be set to the
POWERDOWN state by the Xilinx ISE development software, and will consume no power.
An instantiated transceiver, however, will consume some power, even if it is not engaged
in transmitting or receiving. Therefore, when a transceiver is not to be used for an extended
period of time, the POWERDOWN port should be asserted High to reduce overall power
consumption by the Virtex-II Pro FPGA.
Deasserting the POWERDOWN port restores the transceiver to normal functional status.
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
89, for detailed information on powering instantiated RocketIO transceivers.
www.xilinx.com
1-800-255-7778
Power Conditioning,
Table 3-1, page 25) that allows shutting
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