Clock Dependency - Xilinx RocketIO X User Manual

R
Table 3-3: Supported Standards, Speeds, Bus Widths, and Frequencies for Reference Clocks (Continued)
Supported
Mode Serial
Standard
Number Speed
(1)
28_40
PCI
Express/
Infiniban
d
29_10 PCI
Express/
Infiniban
d
29_20
PCI
Express/
Infiniban
d
29_40
PCI
Express/
Infiniban
d
30_16 OC48 2.4883
30_32 OC48 2.4883
30_8 OC48 2.4883
31_16 OC48 2.4883
31_32 OC48 2.4883
31_8 OC48 2.4883
Notes:
1. Settings optimized for that speed or standard.
2. See Table 2-2, page 46 and
3. Supported internally to the transceiver; other encode/decode schemes supported in the fabric.

Clock Dependency

All signals used by the FPGA fabric to interact between user logic and the transceiver
depend on an edge of USRCLK2 (PMA attribute bus signals are asynchronous
signals all have setup and hold times with respect to this clock. For specific timing values,
see Module 3 of the Virtex-II Pro data sheet. The timing relationships are further discussed
and illustrated in
88
REFCLK
or
TXOUTCLK
BREFCLK (MHz)
(MHz)
2.5 125 125
2.5 62.5 250
2.5 62.5 125
2.5 62.5 125
155.52 155.52
155.52 155.52
155.52 311.04
77.76 155.52
77.76 155.52
77.76 311.04
Table 2-3, page 46 on how to configure the data width for the internal and external bus widths.
Appendix A, "RocketIO X Transceiver Timing Model."
Chapter 3: Clocking and Clock Domains
USRCLK USRCLK2
RXRECCLK
(MHz) (MHz)
125 125
250 125
125 125
125 125
155.52 155.52
155.52 155.52
311.04 155.52
155.52 155.52
155.52 155.52
311.04 155.52
www.xilinx.com
1-800-255-7778
(2)
Internal External
BUSWIDTH BUSWIDTH
(MHz)
(bits) (bits)
62.5 20 40/32
250 20 10/8
125 20 20/16
62.5 20 40/32
155.52 16 16
77.76 16 32
311.04 16 8
155.52 16 16
77.76 16 32
311.04 16 8
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
(2)
Encoding
(3)
None/
8B/10B
None/8B
/10B
None/
8B/10B
None/
8B/10B
None
None
None
None
None
None
These
).