Crc Latency; Ports And Attributes; Tx_Crc_Use; Rx_Crc_Use - Xilinx RocketIO User Manual

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CRC (Cyclic Redundancy Check)

CRC Latency

Enabling CRC increases the transmission latency from TXDATA to TXP and TXN. The
enabling of CRC does not affect the latency from RXP and RXN to RXDATA. The typical
and maximum latencies, expressed in TXUSRCLK/RXUSRCLK cycles, are shown in
Table
Virtex-II Pro Data
Table 2-20: Effects of CRC on Transceiver Latency
CRC Disabled
CRC Enabled
Notes:
1. See
2. This maximum may occur when certain conditions are present, and clock correction and channel
3. To further reduce receive-side latency, refer to

Ports and Attributes

TX_CRC_USE,

RX_CRC_USE

These two attributes control whether the MGT CRC circuitry is enabled or bypassed. When
set to TRUE, CRC is enabled. When set to FALSE, CRC is bypassed and must be
implemented in the FPGA fabric.

CRC_FORMAT

There are four possible CRC modes: USER_MODE, FIBRE_CHAN, ETHERNET, and
INFINIBAND. This attribute is modifiable only for the GT_XAUI and GT_CUSTOM
primitives. Each mode has a Start of Packet (SOP) and End of Packet (EOP) setting to
determine where to start and end the CRC monitoring. USER_MODE allows the user to
define the SOP and EOP by setting the CRC_START_OF_PKT and CRC_END_OF_PKT to
one of the valid K-characters
and TX_CRC_USE. Whenever these attributes are set to TRUE, CRC is used.
The four modes are defined in the subsections following.
USER_MODE
USER_MODE is the simplest CRC methodology. The CRC checks for the SOP and EOP,
calculates CRC on the data, and leaves the four remainders directly before the EOP. The
CRC form for the user-defined mode is shown in
when RXCHECKINGCRC and RXCRCERR are asserted High with respect to the incoming
data.
To check the CRC error detection logic in a testing mode such as serial loopback, a CRC
error can be forced by setting TXFORCECRCERR to High, which incorporates an error into
the transmitted data. When that data is received, it appears "corrupted," and the receiver
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
2-20. For timing diagrams expressing these relationships, please see Module 3 of the
Sheet.
TXDATA to TXP and TXN
in TXUSRCLK Cycles
Typical
Table 2-6 and Table 2-7 for all MGT block latency parameters.
bonding are enabled. If these functions are both disabled, the maximum will be near the typical
values.
(Table B-2, page
www.xilinx.com
Maximum
8 11
14 17
Appendix C, "Related Online Documents."
143). The CRC is controlled by RX_CRC_USE
Figure
(1)
RXP and RXN to RXDATA
in RXUSRCLK Cycles
Typical Maximum
25 42
25 42
2-24, along with the timing for
R
(3)
(2)
(2)
85