Clock Ratio; Digital Clock Manager (Dcm) Examples - Xilinx RocketIO User Manual

Product Not Recommended for New Designs
R
Table 2-3: BREFCLK Pin Numbers
FF672
FF896
FF1152
FF1148
FF1517
FF1704
FF1696

Clock Ratio

USRCLK2 clocks the data buffers. The ability to send/receive parallel data to/from the
transceiver at three different widths requires the user to change the frequency of
USRCLK2. This creates a frequency ratio between USRCLK and USRCLK2. The falling
edges of the clocks must align.
Table 2-4: Data Width Clock Ratios
Notes:
1. Each edge of the slower clock must align with the falling edge of the faster clock.

Digital Clock Manager (DCM) Examples

With at least three different clocking schemes possible on the transceiver, a DCM is the best
way to create these schemes.
Table 2-5
input reference clock for the DCM. The other clocks are generated by the DCM. The DCM
establishes a desired phase relationship between TXUSRCLK, TXUSRCLK2, etc. in the
FPGA core and REFCLK at the pad.
NOTE: The reference clock may be any of the four MGT clocks, including the BREFCLKs.
42
Package
BREFCLK
Pin Number
B14/C14
F16/G16
H18/J18
N/A
E20/D20
G22/F22
N/A
Data Width
1 byte
2 byte
4 byte
shows typical DCM connections for several transceiver clocks. REFCLK is the
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Chapter 2: Digital Design Considerations
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BREFCLK2 BREFCLK
Pin Number Pin Number
C13/B13 AD14/AE14
G15/F15 AH16/AJ16
J17/H17 AK18/AL18
N/A
J20/K20 AR20/AT20
F21/G21 AU22/AT22
N/A
Table 2-4 shows the ratios for each of the three data widths.
Frequency Ratio of USRCLK\USRCLK2
RocketIO™ Transceiver User Guide
Bottom
BREFCLK2
Pin Number
AE13/AD13
AJ15/AH15
AL17/AK17
N/A N/A
AL20/AK20
AT21/AU21
N/A N/A
(1)
1:2
1:1
(1)
2:1
UG024 (v3.0) February 22, 2007