Vhdl - Xilinx RocketIO User Manual

Other Important Design Notes

VHDL

UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
rxisk_reg
aligned_rxisk
byte_sync
end
else
begin
rxdata_reg[15:0] <= rxdata[15:0];
rxisk_reg[1:0]
if ( rxchariscomma3 )
begin
aligned_data[31:0] <= rxdata[31:0];
aligned_rxisk[3:0]
byte_sync
end
else
if ( rxchariscomma1 | byte_sync )
begin
aligned_data[31:0] <= { rxdata_reg[15:0], rxdata[31:16] };
aligned_rxisk[3:0]
byte_sync
end
else
begin
aligned_data[31:0] <= rxdata[31:0];
aligned_rxisk <= rxisk;
end
end
end
endmodule // align_comma_32
-- *
-- ***********************************************************
-- ***********************************************************
-- *
-- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- * SOLUTIONS FOR XILINX DEVICES.
-- * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- * FOR YOUR IMPLEMENTATION.
-- * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- * FOR A PARTICULAR PURPOSE.
-- *
-- * (c) Copyright 2002 Xilinx Inc.
-- * All rights reserved.
-- *
--************************************************************
-- Virtex-II Pro RocketIO comma alignment module
--
-- This module reads RXDATA[31:0] from a RocketIO transceiver
-- and copies it to
-- its output, realigning it if necessary so that commas
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<= 2'b00;
<= 4'b0000;
<= 1'b0;
<= rxisk[1:0];
<= rxisk[3:0];
<= 1'b0;
<= { rxisk_reg[1:0], rxisk[3:2] };
<= 1'b1;
BY PROVIDING THIS DESIGN, CODE,
XILINX EXPRESSLY DISCLAIMS ANY
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