Example 1B: Two-Byte Clock Without Dcm; Example 2: Four-Byte Clock - Xilinx RocketIO User Manual

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Example 1b: Two-Byte Clock without DCM

If TXDATA and RXDATA are not clocked off the FPGA using the respective USRCLK2s,
then the DCM may be removed from the two-byte clocking scheme, as shown in
Figure

Example 2: Four-Byte Clock

If a 4-byte or 1-byte data path is chosen, the ratio between USRCLK and USRCLK2
changes. The time it take for the SERDES to serialize the parallel data requires the change
in ratios.
The DCM example
REFCLK is 156 MHz and USRCLK2_M runs at only 78 MHz, including the clocking for
46
.DSSEN ( 1'b0 ),
.PSCLK ( 1'b0 ),
.PSEN ( 1'b0 ),
.PSINCDEC ( 1'b0 ),
.RST ( 1'b0 ),
.CLK0 ( clk_i ),
.CLK90 ( ),
.CLK180 ( ),
.CLK270 ( ),
.CLK2X ( ),
.CLK2X180 ( ),
.CLKDV ( ),
.CLKFX ( ),
.CLKFX180 ( ),
.LOCKED ( DCM_LOCKED ),
.PSDONE ( ),
.STATUS ( )
);
BUFG buf1 (
.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFG buf2(
.I ( REFCLKIN ),
.O ( REFCLKINBUF )
);
endmodule
2-3:
Note: Implementation tools automatically
instantiate the BUFG. There is no need to
explicitly instantiate in HDL code.
Figure 2-3: Two-Byte Clock without DCM
(Figure 2-4) is detailed for a 4-byte data path. If 3.125 Gb/s is required,
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Chapter 2: Digital Design Considerations
MGT for 2-Byte Data Path (no DCM)
0
IBUFGDS BUFG
REFCLK_P
REFCLK_N
RocketIO™ Transceiver User Guide
GT_std_2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
ug024_02b_062404
UG024 (v3.0) February 22, 2007