Crc_Start_Of_Packet; Crc_End_Of_Packet; Rxcheckingcrc, Rxcrcerr; Txforcecrcerr, Tx_Crc_Force_Value - Xilinx RocketIO User Manual

R
The CRC checks the LNH (Link Next Header) of the LRH. LRH is shown in
with the bits the CRC uses to evaluate the next packet.
Because of the complexity of the CRC algorithms and implementations, especially with Infiniband,
a more in-depth discussion is beyond the scope of this manual.

CRC_START_OF_PACKET,

CRC_END_OF_PACKET

When implementing USER_MODE CRC, Start of Packet (SOP) and End of Packet (EOP) must be
defined for the CRC logic. These delimiters must be one of the defined K-characters (see
page
otherwise, the CRC will mistake the CCS or IDLE for SOP/EOP.
RXCHECKINGCRC,
RXCRCERR
These two signals are status ports for the CRC circuitry.
RXCHECKINGCRC is asserted within several USRCLKs of the EOF being received from
RXDATA. This signals that the CRC circuitry has identified the SOF and the EOF.
If a CRC error occurred, RXCRCERR will be asserted at the same time that RXCHECKINGCRC
goes High.
TXFORCECRCERR,
TX_CRC_FORCE_VALUE
To test the CRC logic in either the MGT or the FPGA fabric, TXFORCECRCERR and
TX_CRC_FORCE_VALUE may be used to invoke a CRC error. When TXFORCECRCERR is
asserted High for at least one USRCLK2 cycle during data transmission (between SOP and EOP),
the CRC circuitry is forced to XOR TXDATA with TX_CRC_FORCE_VALUE, creating a bit error.
This should cause the receiver to register that a CRC error has occurred.

RocketIO CRC Support Limitations

There are limitations to the CRC support provided by the RocketIO transceiver core:
•
88
− B1
B B1
0 7
1 1 IBA Global Packet
B1 , B1
1 0
1 0 IBA Local Packet
0 1 Raw Packet (CRC does not insert remainder)
0 0 Raw Packet (CRC does not insert remainder)
Figure 2-27: Local Route Header
Note:
Minimum data length for this mode is defined by the protocol requirements.
141). These must be different than a clock correction sequence (CCS) or IDLE sequence;
Note:
These attribute are not applicable to the other CRC formats.
RocketIO CRC support is implementable for single-channel use only. Computation and byte-
striping of CRC across multiple bonded channels is not supported. For that usage, the CRC
logic can be implemented in the FPGA fabric.
www.xilinx.com
1-800-255-7778
Chapter 2: Digital Design Considerations
B B B B
0 2 3 4
RocketIO™ Transceiver User Guide
Figure 2-27, along
B B
5 6 7
UG024_15_020802
Table B-2,
UG024 (v2.3.2) June 24, 2004