Figure 3-9: Txoutclk 2:2:1; Figure 3-10: Rxrecclk 2:2:1 - Xilinx RocketIO X User Manual
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- User manual (152 pages) ,
- User manual (156 pages) ,
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Clock Domain Architecture
TXOUTCLK
USRCLK
USRCLK2 and
User Logic
RXRECCLK
USRCLK
USRCLK2 and
User Logic
*RXRECCLK should only drive the receive clocks
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
Figure 3-9: TXOUTCLK 2:2:1
sing option BREFCLK
2:2:1 for TX
DV ratio = 2
Figure 3-10: RXRECCLK 2:2:1
www.xilinx.com
1-800-255-7778
DCM
CLKIN
CLK180
CLKDV
CLK0
CLKFB
BUFG
User
TX & RX
Logic
DV ratio = 2
DCM
CLKIN
CLK180
CLKDV
CLK0
CLKFB
BUFG
User
TX
Logic
RX
DCM
CLKIN
CLK180
CLKDV
CLK0
CLKFB
R
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
UG035_CH3_17_060304
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
UG035_CH3_18_111604
79
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