Table 4-4: Cdr Parameters - Xilinx RocketIO User Manual

R

Table 4-4: CDR Parameters

A sufficient number of transitions must be present in the data stream for CDR to work
properly. The CDR circuit is guaranteed to work with 8B/10B encoding. Further, CDR
requires approximately 5,000 transitions upon power-up to guarantee locking to the
incoming data rate. Once lock is achieved, up to 75 missing transitions can be tolerated
before lock to the incoming data stream is lost.
An additional feature of CDR is its ability to accept an external precision clock, REFCLK,
which either acts to clock incoming data or to assist in synchronizing the derived
RXRECCLK. REFCLK acts either to clock incoming data or to assist in synchronizing the
derived RXRECCLK.
For further clarity, the TXUSRCLK is used to clock data from the FPGA core to the TX
FIFO. The FIFO depth accounts for the slight phase difference between these two clocks. If
the clocks are locked in frequency, then the FIFO acts much like a pass-through buffer.
88
Parameter
Frequency Serial input
Range differential
(RXP/RXN)
Frequency
Offset
T REFCLK duty cycle
DCREF
T /T REFCLK rise and
RCLK FCLK
fall time (see
Virtex-II Pro Data
Sheet, Module 3)
T REFCLK total jitter
GJTT
T Clock recovery
LOCK
frequency
acquisition time
T
UNLOCK
PLL length
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Chapter 4: Analog Design Considerations
Min Typ Max
311 1,562.5
45 50 55
75
40
10
75
transitions
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
Units Conditions
MHz
ppm
%
ps Between 20%
and 80% voltage
levels
ps Peak-to-peak
µs
cycles
non- Requirement
when bypassing
8B/10B