Half-Rate Clocking Scheme - Xilinx RocketIO User Manual

Product Not Recommended for New Designs
R

Half-Rate Clocking Scheme

Some applications require serial speeds between 600 Mb/s and 1 Gb/s. (Refer to
when considering running in this serial range.) The transceiver attribute SERDES_10B,
which sets the REFCLK multiplier to 10 instead of 20, enables the half-rate speed range
when set to TRUE. With this configuration, the clocking scheme also changes. The figures
below illustrate the three clocking scheme waveforms when SERDES_10B = TRUE.
Clocks for 1-Byte Data Path
(SERDES_10B = TRUE)
Figure 2-6: One-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 2-Byte Data Path
(SERDES_10B = TRUE)
Figure 2-7: Two-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 4-Byte Data Path
(SERDES_10B = TRUE)
Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE
54
IBUFGDS
REFCLK
REFCLK_P
REFCLK_N
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
IBUFGDS
REFCLK_P
REFCLK
REFCLK_N
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
IBUFGDS
REFCLK_P
REFCLK
REFCLK_N
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
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Chapter 2: Digital Design Considerations
CLKDV = divide by 2
BUFG
DCM
CLKIN CLKDV
CLKFB
RST CLK0
MGT clock input invert-
BUFG
ers (acceptable skew)
CLKDV = divide by 2
DCM
CLKIN
CLKDV
BUFG
CLK0
CLKFB
BUFG
CLKDV = divide by 4
CLK_FX = divide by 2
DCM
CLKIN CLK_FX180
BUFG
CLKDV
BUFG
CLK0
CLKFB
BUFG
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
XAPP572
GT_std_1
0
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
UG024_29_013103
GT_std_2
0
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
UG024_30_013103
GT_std_4
0
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
UG024_31_013103