Txdigsw; Txanasw; Rxdivratio[13:0]; Table C-19: Txdigsw Definition - Xilinx RocketIO X User Manual

Register Definition

TXDIGSW

TXDIGSW selects the source of 1.5V transmit digital power supply. The default is
primitive dependent. The transmit digital power supply selection is defined as follows:

Table C-19: TXDIGSW Definition

TXANASW

TXANASW selects the source of 1.5V transmit analog power supply. The default is
primitive dependent. The transmit analog power supply selection is defined as follows:

Table C-20: TXANASW Definition

RXDIVRATIO[13:0]

RXDIVRATIO[13:0] controls the divider ratios for RXCLK0, RXRECCLK, and the PLL
clock multiplier ratio of the receiver relative to the receiver bit rate. In addition,
RXDIVRATIO[13] controls a programmable divide by 2 on the BREFCLK input to the
phase detector. The defaults for these are primitive dependent, based on reference clock
frequency and encoding.

Table C-21: RX Clock Multiplier Ratio Definition

RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
TXDIGSW
0
1
TXANASW
0
1
RXDIVRATIO[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
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Transmit Digital Supply
Regulated (from 2.5V)
Unregulated (from 1.5V)
Transmit Analog Supply
Regulated (from 2.5V)
Unregulated (from 1.5V)
Divider
÷ 8
÷ 8.25
÷ 10
Reserved
÷ 16
÷ 16.5
÷ 20
Reserved
÷ 32
÷ 33
÷ 40
Reserved
R
155