Half-Rate Clocking Scheme - Xilinx RocketIO User Manual

Clocking

Half-Rate Clocking Scheme

Some applications require serial speeds between 600 Mb/s and 1 Gb/s. The transceiver attribute
SERDES_10B, which sets the REFCLK multiplier to 10 instead of 20, enables the half-rate speed
range when set to TRUE. With this configuration, the clocking scheme also changes. The figures
below illustrate the three clocking scheme waveforms when SERDES_10B = TRUE.
Clocks for 1-Byte Data Path
(SERDES_10B = TRUE)
Figure 2-6: One-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 2-Byte Data Path
(SERDES_10B = TRUE)
Figure 2-7: Two-Byte Data Path Clocks, SERDES_10B = TRUE
Clocks for 4-Byte Data Path
(SERDES_10B = TRUE)
Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
IBUFGDS
REFCLK
REFCLK_P
REFCLK_N
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK_P
REFCLK
REFCLK_N
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK_P
REFCLK
REFCLK_N
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
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CLKDV = divide by 2
BUFG
DCM
CLKIN CLKDV
CLKFB
RST CLK0
BUFG
CLKDV = divide by 2
IBUFGDS
DCM
CLKIN
CLKDV
CLK0
CLKFB
CLKDV = divide by 4
CLK_FX = divide by 2
IBUFGDS
DCM
CLKIN CLK_FX180
CLKDV
CLK0
CLKFB
GT_std_1
0 REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
MGT clock input invert-
ers (acceptable skew)
UG024_29_013103
GT_std_2
0 REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
BUFG
BUFG
UG024_30_013103
GT_std_4
0
REFCLKSEL
REFCLK
TXUSRCLK
RXUSRCLK
BUFG
TXUSRCLK2
RXUSRCLK2
BUFG
BUFG
UG024_31_013103
R
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