Clock And Data Recovery - Xilinx RocketIO User Manual

Product Not Recommended for New Designs
R
Deterministic Jitter (DJ) is data pattern dependant jitter, attributed to a unique source (e.g.,
Inter Symbol Interference (ISI) due to loss effects of the media). DJ is linearly additive.
Random Jitter (RJ) is due to stochastic sources, such as substrate, power supply, etc. RJ is
additive as the sum of squares, and follows a bell curve.

Clock and Data Recovery

The serial transceiver input is locked to the input data stream through Clock and Data
Recovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and
falling edges of incoming data and derives a clock that is representative of the incoming
data rate.
The derived clock, RXRECCLK, is presented to the FPGA fabric at 1/20th the incoming
data rate (whether full-rate or half-rate). This clock is generated and remains locked as
long as it remains within the specified component range. This range is shown in
A sufficient number of transitions must be present in the data stream for CDR to work
properly. The CDR circuit is guaranteed to work with 8B/10B encoding. Further, CDR
requires approximately 5,000 transitions upon power-up to guarantee locking to the
incoming data rate. Once lock is achieved, up to 75 missing transitions can be tolerated
before lock to the incoming data stream is lost.
Table 3-4: CDR Parameters
Frequency Range
TDCREF
TRCLK/TFCLK
TGJTT
TLOCK
TUNLOCK
Notes:
1. BREFCLK for speeds of 2.5 Gb/s or greater.
2. Jitter measured at BGA ball.
3. T
108
Parameter
Serial input, diff.
(RXP/RXN)
(1)
REFCLK duty cycle
(1)
REFCLK rise and
fall time (see
Virtex-II Pro Data
Sheet, Module 3)
(1)
REFCLK total
(2)
jitter, peak-to-peak
(3)
Clock recovery
frequency acquisition
time
PLL length
depends on serial speed and length/type of sequence used.
LOCK
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Chapter 3: Analog Design Considerations
Min Typ Max Units
300 1,562.5 MHz
45 50 55 %
600 1000 ps
40 ps
50 ps
120 ps
10 µs
cycles
75 non-
transitions
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Table 3-4.
Conditions
Between 20%
and 80% voltage
levels
3.125 Gb/s
2.5 Gb/s
1.06 Gb/s
From system
reset. Much less
time is needed to
lock if loss of
sync occurs
(T ), which is
phase
described in Data
Sheet Module 3.
Requirement
when bypassing
8B/10B