Table C-5: Txclk0 Divider Ratio Definition; Table C-6: Txoutclk Divider Ratio Definition - Xilinx RocketIO X User Manual
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Table C-4: TX Clock Multiplier Ratio Definition (Continued)
Table C-5: TXCLK0 Divider Ratio Definition
Table C-6: TXOUTCLK Divider Ratio Definition
150
TXDIVRATIO[3:0]
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TXDIVRATIO[5:4]
00
01
10
11
TXDIVRATIO[9:6]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
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Appendix C: PMA Attribute Programming Bus
Divider
÷ 8
÷ 8.25
÷ 10
Reserved
÷ 16
÷ 16.5
÷ 20
Reserved
Reserved
Reserved
Reserved
Reserved
Divider
÷ 8
÷ 8.25
÷ 10
Reserved
Divider
÷ 4
÷ 4.125
÷ 5
Reserved
÷ 8
÷ 8.25
÷ 10
Reserved
÷ 16
÷ 16.5
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
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