Example 3: One-Byte Clock; Figure 3-3: One-Byte Clock - Xilinx RocketIO User Manual

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Example 3: One-Byte Clock

This is the 1-byte wide data path clocking scheme example. USRCLK2_M is twice as fast as
USRCLK_M. It is also phase-shifted 180° for falling edge alignment.
Clocks for 1-Byte Data Path
VHDL Template
46
.CLK2X180
.CLKDV
.CLKFX
.CLKFX180
.LOCKED
.PSDONE
.STATUS
);
BUFG buf1 (
.I ( clkdv2 ),
.O ( USRCLK2_M )
);
BUFG buf2 (
.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFG buf3(
.I ( REFCLKIN ),
.O ( REFCLKINBUF )
endmodule
REFCLK
TXUSRCLK
REFCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2

Figure 3-3: One-Byte Clock

-- Module: ONE_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 1-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity ONE_BYTE_CLK is
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Chapter 3: Digital Design Considerations
( ),
( clkdv2 ),
( ),
( ),
( DCM_LOCKED ),
( ),
( )
);
MGT + DCM for 1-Byte Data Path
DCM
IBUFG
CLKIN CLK2X180
CLKFB
RST
CLK0
RocketIO™ Transceiver User Guide
GT_std_1
0
REFCLKSEL
BUFG
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
BUFG
UG024_04_020802
UG024 (v1.5) October 16, 2002